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devices incorporated video imaging products 1 LF3370 high-definition video format converter 08/21/2000Clds.3370-e colorspace converter/ key scaler input de-multiplexer section 55-tap half-band interpolation/ decimation filters output multiplexer section b 12-0 c 12-0 a 12-0 d 12-0 x 12-0 y 12-0 w 12-0 z 12-0 1k x 13-bit look-up-tables input bias adders output bias adders features LF3370 high-definition video format converter devices incorporated q q q q q 83 mhz data rate for hdtv applications q q q q q supports multiple video formats bi-directional conversions: - 4:2:2:4 - 4:4:4:4 - r/g/b/key - y/u/v/key q q q q q multiplexed and non-multiplexed i/o data q q q q q user-programmable: - 3 x 3 colorspace converter - lut for gamma correction - i/o bias compensation - bypass capability q q q q q 13-bit data path, colorspace converter coefficients and key channel scaling coefficients q q q q q 160-lead pqfp description the LF3370 is a video format converter capable of operating at hdtv data rates. this device converts to and from any of the various sdtv/hdtv digital video formats by utilizing an internal 3 x 3 matrix multiplier and two 1:2 interpolation/2:1 decimation half-band filters. using the input demultiplexer and output multiplexer, the LF3370 can accept and output interleaved or non-interleaved video. for example, r/g/b/key data can be color space converted to y/u/v/key and down-con- verted to 4:2:2:4. by re-arranging the order of the functional sec- tions, the opposite conversion can be achieved. the coefficients for the 3 x 3 matrix multiplier are fully user programmable to sup- port a wide range of color space conversions. the two interpola- tion/decimation half-band filters are fully compliant with smpte 260m. input and output bias adders are included for removing or adding a user-defined bias into the video signal. in addition, three pro- grammable 1k x 13-bit look-up tables (luts) have also been included for various uses such as gamma correction. a scaler has been included on the key channel for scaling to a desired magnitude using user programmable coeffi- cients. input signals can also be forced to user-defined levels for horizontal blanking. furthermore, a round/ select/limit (rsl) circuitry is provided at the end of various stages to provide the best possible conversions without color viola- tions. for additional flexibility, all sections can be individually bypassed using an internal pro- grammable length delay. all control and coefficient registers are loaded through the lf inter- face?. this device operates at 3.3 v (5 v tolerant i/o) and is available in 160-lead pqfp package. LF3370 b lock d iagram
devices incorporated LF3370 high-definition video format converter 2 08/21/2000Clds.3370-e video imaging products f igure 1. LF3370 f unctional b lock d iagram (h alf -b and f ilter to c olorspace a rrangement ) half-band filter/ interpolator half-band filter/ interpolator 1k x 13-bit lut* 1k x 13-bit lut* 1k x 13-bit lut* chroma half-band filter / interpolator output mux 3 x 3 matrix multiply / key scaler output bias adder output bias adder output bias adder colorspace converter key scaler 2 1 input demux input bias adder input bias adder input bias adder 1k x 13-bit lut* 1k x 13-bit lut* 1k x 13-bit lut* 2 13 13 20 13 20 13 35 13 13 13 13 13 35 13 13 13 13 13 13 13 13 13 13 13 13 wout 12-0 xout 12-0 yout 12-0 zout 12-0 rsl 1-0 round select limit round select limit 20 13 20 13 round select limit round select limit 20 round select limit 20 round select limit 13 13 1 3 inbias 1-0 13 13 13 13 13 13 13 ain 12-0 bin 12-0 cin 12-0 din 12-0 13 13 13 13 2 oe 3 2 3-5 coefficient banks 0-9 2 ca 1-0 2 2 outbias 1-0 lf interface cf 12-0 ld 13 pause sync hblank datapass reset flag generator hf 0 hf 1 clk input look-up-table* output look-up-table* configuration and control registers note: numbers in registers indicate number of pipeline delays which is also equivalent to number of pipeline delays through that particular functional block * up to one look-up-table may be used per data path. the inherent delay through the look-up-table is two regardless of whether it is used or not.
devices incorporated video imaging products 3 LF3370 high-definition video format converter 08/21/2000Clds.3370-e f igure 2. LF3370 f unctional b lock d iagram (c olorspace to h alf -b and f ilter a rrangement ) 1k x 13-bit lut* 1k x 13-bit lut* 1k x 13-bit lut* output mux output bias adder output bias adder output bias adder 2 1 input demux input bias adder input bias adder input bias adder 1k x 13-bit lut* 1k x 13-bit lut* 1k x 13-bit lut* 2 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 wout 12-0 xout 12-0 yout 12-0 zout 12-0 rsl 1-0 13 13 13 13 1 inbias 1-0 13 13 13 13 13 13 13 ain 12-0 bin 12-0 cin 12-0 din 12-0 13 13 13 13 2 oe 2 3-5 half-band filter/ decimator half-band filter/ decimator chroma half-band filter / interpolator 20 20 35 35 round select limit round select limit 2 2 outbias 1-0 lf interface cf 12-0 ld 13 pause 3 x 3 matrix multiply / key scaler colorspace converter key scaler 20 20 round select limit round select limit 20 round select limit 20 round select limit 3 3 coefficient banks 0-9 ca 1-0 2 sync hblank datapass reset flag generator hf 0 hf 1 clk input look-up-table* output look-up-table* configuration and control registers note: numbers in registers indicate number of pipeline delays which is also equivalent to number of pipeline delays through that particular functional block * up to one look-up-table may be used per data path. the inherent delay through the look-up-table is two regardless of whether it is used or not. 13 13 13 13
devices incorporated LF3370 high-definition video format converter 4 08/21/2000Clds.3370-e video imaging products counter reaches its user-defined terminal count; a high to low transition of hblank and/or reset will reset the flags. inbias 1-0 input bias control inbias 1-0 determines which of the four user-programmable input bias registers are used to sum with the input data. outbias 1-0 output bias control outbias 1-0 determines which of the four user-programmable output bias registers are used to sum with the output data. rsl 1-0 round/select/limit control rsl 1-0 determines which of the user- programmable round/select/limit registers (rsl registers) are used in the rsl circuitry. a value of 00 on rsl 1-0 selects rsl register 0. a value of 01 selects rsl register 1 and so on. rsl 1-0 is latched on the rising edge of clk. oe output enable when oe is low, w 12-0 , x 12-0 , y 12-0 , and z 12-0 are enabled for output. when oe is high, w 12-0 , x 12-0 , y 12-0 , and z 12-0 are placed in a high- impedance state. pause lf interface tm pause when pause is high, the LF3370 lf interface tm loading sequence is halted until pause is returned to a low state. this effectively allows the user to load coefficients and control registers at a slower rate than the master clock. reset reset reset is used to reset all program- mable flags and line up clock edges during single muxed input or single muxed output events. reset is used at power up or just after device configuration. signal definitions power v cc and gnd +3.3 v power supply. all pins must be connected. clock clk master clock the rising edge of clk strobes all enabled registers. to guarantee data integrity, a minimum of 10khz must be maintained. inputs a 12-0 , b 12-0 , c 12-0, d 12-0 data inputs a 12-0 , b 12-0 , c 12-0 , and d 12-0 are the 13-bit registered data input ports. data is latched on the rising edge of clk. cf 12-0 coefficient input cf 12-0 is used to address and load colorspace/key scaler coefficient banks, round/select/limit registers, and configuration registers. data present on cf 12-0 is latched into the lf interface tm on the rising edge of clk when ld is low. ca 1-0 coefficient address ca 1-0 determines which of the four user-programmable colorspace/key scaler coefficients are used. outputs w 12-0 , x 12-0 , y 12-0 , z 12-0 data outputs w 12-0 , x 12-0 , y 12-0 , and z 12-0 are the 13-bit registered data output ports. the data present on the output ports will correspond to the appropiate input data, based on the user-progammable configuration. controls ld coefficient load when ld is low, data on cf 12-0 is latched into the LF3370 lf interface tm on the rising edge of clk. when ld is high, data is not loaded into the lf interface tm . when enabling the lf interface tm for data input, a high to low transition of ld is required in order for the input circuitry to function properly. therefore, ld must be set high immediately after power up to ensure proper operation of the input circuitry. sync synchronization for data alignment sync control signal is required to properly synchronize the input demultiplexer, output multiplexer, and halfband filters to the data flowing through the LF3370. a high to low transition tells the core which sample corresponds to a cb/cr sample for proper de-multiplexing and multiplexing. this signal will also synchronize the half-band filters into a decimation/interpolation sequence. datapass datapass mode datapass is used to place the LF3370 in a mode of operation that allows the user to pass data through the core (input/output bias adders, luts, hafband interpolator/ decimator, colorspace/key scaler) without any processing. hblank horizontal blanking control hblank is used for data replace- ment corresponding to user-selectable blanking levels. a high to low transition resets the counter and the hfx flags. hf 1 /hf 0 hblank flags hf 1 and hf 0 are two general purpose flags used to indicate when a 20-bit
devices incorporated video imaging products 5 LF3370 high-definition video format converter 08/21/2000Clds.3370-e LF3370 device initialization this section explains how to initialize the device for proper operation. it also serves as a summary of all conditions that should be considered before using the device or for troubleshooting. configuration register 0 and configura- tion register 1 must be loaded before operation of the device. if core bypassing is desired, configuration register 2 must be loaded before use. if use of the half- band filters is desired, at least one half- band filter rsl register set must be loaded and selected for each half-band filter. if use of the matrix multiplier/key scaler is desired, at least one matrix multiplier/ key scaler rsl register set and coefficient must be loaded and selected for each channel. if use of the input bias adder is desired, at least one input bias adder register must be loaded and selected before use. if use of the output bias adder is desired, at least one output bias adder register must be loaded and selected before use. if use of the look-up table is desired, the look-up table must be loaded before use. when using a single channel input or output with interleaved video, sync and reset should be used for proper initializa- tion as shown in figure 4. if 12 bits or less input data is desired, the input data should be shifted so the msbs are aligned. input demultiplexer the input demultiplexer section acts as a buffer between the users datapath and the LF3370s core. data may be presented on input ports a 12-0 , b 12-0 , and c 12-0 as three channels of non-interleaved input data, one channel non-interleaved and one channel interleaved input data, or one channel of interleaved data (see table 1 for various video input schemes). d 12-0 is the key channel input port; the key channel simply gets passed through the input demultiplexer with a latency that matches the other three channels. * not all input/output combinations are valid. if single channel interleaved video is used on either the input or output, the core clock will be running at clk/2. thus the maximum input, output, and core data rate must be considered. input input format channel 4:4:4:4* 4:2:2:4* 4:2:2:4 4:2:2:4 a 12-0 r y y y/cr/cb b 12-0 g cr cr/cb n/a c 12-0 b cb n/a n/a d 12-0 key key key key t able 1. i nput /o utput f ormats output output format channel 4:4:4:4* 4:2:2:4* 4:2:2:4 4:2:2:4 w 12-0 r y y y/cr/cb x 12-0 g cr cr/cb n/a y 12-0 b cb n/a n/a z 12-0 key key key key f igure 3. i nput and o utput f ormats 12 11 10 2 1 0 C2 0 (sign) 2 C1 2 C2 2 C10 2 C11 2 C12 coefficient data 12 11 10 2 1 0 C2 12 (sign) 2 11 2 10 2 2 2 1 2 0 12 11 10 2 1 0 C2 12 (sign) 2 11 2 10 2 2 2 1 2 0 input data output data input bias adder/output bias adder matrix multiplier/key scaler f 19 f 18 f 17 f 2 f 1 f 0 C2 15 (sign) 2 14 2 13 2 C2 2 C3 2 C4 f 19 f 18 f 17 f 2 f 1 f 0 C2 13 (sign) 2 12 2 11 2 C4 2 C5 2 C6 *matrix multiplier output *key scaler output 12 11 10 2 1 0 C2 12 (sign) 2 11 2 10 2 2 2 1 2 0 input data *format of matrix multiplier/key scaler ouput feeding the rsl circuitry. f 19 -f 0 corresponds to 20 msbs of which a 13-bit window can be selected from f 19 -f 4 . half-band filter **filter output (non-interpolate) **filter output (interpolate) 12 11 10 2 1 0 C2 12 (sign) 2 11 2 10 2 2 2 1 2 0 input data *format of half-band filter ouput feeding the rsl circuitry. f 19 -f 0 corresponds to 20 msbs of which a 13-bit window can be selected from f 19 -f 4 (see table 3). f 19 f 18 f 17 f 2 f 1 f 0 C2 12 (sign) 2 11 2 10 2 C5 2 C6 2 C7 f 19 f 18 f 17 f 2 f 1 f 0 C2 13 (sign) 2 12 2 11 2 C4 2 C5 2 C6
devices incorporated LF3370 high-definition video format converter 6 08/21/2000Clds.3370-e video imaging products if video data is non-interleaved and presented to input ports a 12-0 , b 12-0 , and c 12-0 , no demultiplexing is performed. the three channels are passed unmodified into the LF3370 core with a delay of 3 clk cycles. for this operation, bits 0 and 1 must both be set to 1 in configuration register 0 (see table 5). if video data is on two channels (see figure 4), one channel of non-interleaved video and one channel of interleaved video, it is assumed that non-interleaved video is presented to input port a 12-0 (i.e., luma) and interleaved video is presented to input port b 12-0 (i.e., chroma). the input demultiplexer, in this case, sepa- rates video data on b 12-0 and outputs two channels of separated video into the LF3370 core with a delay of 4 clk cycles. for this operation, bit 0 must be set to 0 and bit 1 must be set to 1 in configuration register 0 (see table 5). if 4:2:2 video data is on one channel interleaved (see figure 5), it is assumed that interleaved video is presented to input f igure 4. i nput p rocessing 4:2:2:4 (i nterleaved c hroma on c hannel b) clk 1 2 3 demultiplexed input data (output of demux section) a 12-0 5 6 7 8 10 13 y 0 y 1 y 2 y 3 y 4 y 5 y 6 911 sync y 7 y 8 y 9 a' 12-0** c' 12-0** d' 12-0** b' 12-0** 41214 d 12-0 y 10 y 11 y 12 17 15 16 18 * b 12-0 cb 0 cr 0 cb 2 cr 2 cb 4 cr 4 cb 6 cr 6 cb 8 cr 8 cb 10 cr 10 cb 12 k 0 k 1 k 2 k 3 k 4 k 5 k 6 k 7 k 8 k 9 k 10 k 11 k 12 cr' 0 cr' 2 cr' 4 cr' 6 cb' 0 cb' 2 cb' 4 cb' 6 y' 0 y' 1 y' 2 y' 3 y' 4 y' 5 y' 6 y' 7 y' 8 k' 0 k' 1 k' 2 k' 3 k' 4 k' 5 k' 6 k' 7 k' 8 cr' 6 cb' 6 f igure 5. i nput p rocessing 4:2:2:4 (i nterleaved l uma /c hroma on c hannel a) clk reset 1 2 3 core clock (internally generated and synchronized to clk by reset) used only when single channel interleaved input or output vi deo is used. demultiplexed input data (output of demux section) a 12-0 5 6 7 8 10 13 cb 0 y 0 cr 0 y 1 cb 2 y 2 cr 2 911 clk/2* sync y 3 cb 4 y 4 a' 12-0** c' 12-0** cr' 0 d' 12-0** b' 12-0** cb' 0 41214 d 12-0 k 0 k 1 k 2 k 3 k 4 y' 0 y' 1 y' 2 k' 0 k' 1 k' 2 cr' 1 cb' 1 k 5 y' 3 k' 3 cr 4 y 5 cb 6 17 15 16 18 * **
devices incorporated video imaging products 7 LF3370 high-definition video format converter 08/21/2000Clds.3370-e port a 12-0 . the input demultiplexer, in this case, separates video data on a 12-0 and outputs three channels of separated video into the LF3370 core with a delay of 5 clk cycles. in this case, the core will run at half of the clk rate and valid data will be output at at half of the clk rate. for this operation, bit 0 must be set to 1 and bit 1 must be set to 0 in configuration register 0 (see table 5). all input demultiplexing operations are controlled by the high to low transi- tions of sync which synchronizes the LF3370 core to the multiplexed input data (see sync discussion). it is important that unused input ports be set either high or low. output multiplexer the output multiplexer section can be configured in various ways to accommo- date the video system. bits 2 and 3 of configuration register 0 determines the number of output channels that the LF3370 will drive. z 12-0 is the key channel output port; the key channel simply gets passed through the output multiplexer with a latency that matches the other three channels. if three separate output channels of non- interleaved video are desired, no multi- plexing is performed. the three channels are passed through the output multi- plexer unmodified on the output ports w 12-0 , x 12-0 , and y 12-0 with a delay of 2 clk cycles. for this operation, bits 2 and 3 must both be set to 1 in configuration register 0 (see table 5). if one channel of non-interleaved video (i.e., luma) and one channel of inter- leaved video (i.e., chroma) is desired (see figure 6), non-interleaved video will be driven to the output port w 12-0 and interleaved video will be driven to the output port x 12-0 with a delay of 2 clk cycles. for this operation, bit 2 must be set to 0 and bit 3 must be set to 1 in configu- ration register 0 (see table 5). if three channels of interleaved 4:2:2 video is desired (see figure 7), interleaved video will be driven to the output port w 12-0 with a delay of 4 clk cycles. for this operation, bit 2 must be set to 1 and bit 3 must be set to 0 in configuration register 0 (see table 5). all output multiplexing operations are controlled by the high to low transi- tions of sync which synchronizes the multiplexed output data to the LF3370 core (see sync discussion). sync sync control signal is required to properly synchronize the input demultiplexer, output multiplexer, and halfband filters to the data flowing through the LF3370. a high to low transition on sync control signal is needed to initialize the device to mark the beginning of valid data. in addition, if 4:2:2 interleaved video data is desired for input or output, a high to low transition on sync must be registered by a simultaneous rising edge of clk and clk/2. clk/2 is an internal clock that must be synchronized to clk f igure 6. o utputting 4:2:2:4 (i nterleaved c hroma on c hannel x) clk there will be a high to low transition on every cb sample w 12-0 y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 0 (output sync)* y 10 y 11 y 12 * z 12-0 y 13 y 14 y 15 y 16 y 17 cb 0 cr 0 cb 2 cr 2 cb 4 cr 4 cb 6 cr 6 cb 8 cr 8 cb 10 cr 10 cb 12 cr 12 cb 14 cr 14 cb 16 cr 16 k 0 k 1 k 2 k 3 k 4 k 5 k 6 k 7 k 8 k 9 k 10 k 11 k 12 k 13 k 14 k 15 k 16 k 17 x 12-0 f igure 7. o utputting 4:2:2:4 (i nterleaved l uma /c hroma on c hannel w) clk there will be a high to low transition on every cb sample w 12-0 cb 0 y 0 cr 0 y 1 cb 2 y 2 cr 2 y 3 cb 4 y 4 y 0 (output sync)* cr 4 y 5 cb 6 * z 12-0 y 6 cr 6 y 7 cr 8 y 8 k 0 k 1 k 2 k 3 k 4 k 5 k 6 k 7 k 8
devices incorporated LF3370 high-definition video format converter 8 08/21/2000Clds.3370-e video imaging products by use of reset only if the core is running at half the rate of clk (see reset discussion). furthermore, sync is used to identify one interleaved data set from another. for example, in the case of interleaved chroma, cb and cr samples must be properly demultiplexed and synchro- nized for proper processing. to differentiate a cb sample from cr, there needs to be a high to low transition on sync on the first cb sample (see figure 4 and figure 5); sync can also be toggled on every cb sample for re- synchronization. in the case that cb is the first valid data word, sync may be used only once in device initialization and kept low until re- synchronization is desired. therefore, when there is a high to low transition on sync, the following is assumed: cb will occur on the next rising clock edge, cb will occur every two clock cycles if interleaved chroma is presented to the input port b 12-0 , cb will occur every 4 clock cycles if single channel 4:2:2 inter- leaved video is presented to the input port a 12-0 . sync control signal is also used to synchronize the interpolation/decimation output data from the half-band filter to the output multiplexer. reset reset should be used when initializing the device for proper operation. it is used to synchronize the LF3370 core clock to the master clock. in the case that single channel 4:2:2 interleaved video data is desired either on the input or output, thus using only one input or one output port (not including key data), the internal clock rate will be half (clk/2) of the master clock rate (clk). in this case, reset is needed to synchronize the rising edge of clk/2 to a known rising edge of clk (see figure 4). for example, after configuring the LF3370 and before streaming valid data through the part, a reset event should be used to align the clock edges (see figure 5). furthermore, reset will clear hf 0 and hf 1 . a low state detected on reset on a rising edge of clock will clear flags hf 0 and hf 1 on the following rising edge of clock. please note hblank should be used to clear hf 0 and hf 1 during normal operation (see hblank discussion). hblank hblank is used to replace portions of the input data with user-defined blanking levels. when hblank is low, blanking level words are injected into the data stream immediately after the input lut section regardless of this section being used or not and immediately before the matrix multiplier or half-band filter section. during the duration hblank is f igure 10. hblank and c ounter clk hblank 1 2 3 data values at output of input lut section 5 6 7 8 10 13 911 hf 0 hf 1 41214 20-bit counter 17 16 18 * 0 123 4 5 6 78 9 10 0 1 4 5 23 15 d n+3 d n+4 d n+5 d n+6 d n+7 d n+8 d n+9 d n+10 d n+11 d n+3 d n+4 d n+5 d n+6 d n+7 d n+8 d n+9 d n+10 d n+11 d n+3 d n+4 d n+5 d n+6 d n+7 d n+8 d n+9 d n+10 d n+11 d n+3 d n+4 d n+5 d n+6 d n+7 d n+8 d n+9 d n+10 d n+11 a' 12-0* c' 12-0* d' 12-0* b' 12-0* d n hblank word a d n d n d n hblank word b hblank word c hblank word d hblank word a hblank word b hblank word c hblank word d in this example, hf 0 count value is set to 3 and hf 1 count value is set to 5 f igure 9. o utput b ias f igure 8. i nput b ias r0 r3 13 2 13 inbias 1-0 13 13 from input demux r0 r3 13 2 outbias 1-0 13 13 from core
devices incorporated video imaging products 9 LF3370 high-definition video format converter 08/21/2000Clds.3370-e low, blanking level words are continu- ally injected with user-defined blanking words. blanking words are injected on the next rising clock edge when hblank is low. in addition, hblank clears flags hf 0 and hf 1 and resets a 20-bit incrementing counter (0 - 1,048,575). if a high to low transition on hblank is detected on a rising edge of clock, hf 0 and hf 1 are cleared and the counter is reset on the following rising edge of clock (see figure 10). key channel blanking may be independently enabled or disabled using congifuration register 1 (see table 6). hf 0 /hf 1 and counter hf 0 and hf 1 are two independent flags that are set when the pre-programmed hf 0 or hf 1 count value is equal to the 20- bit incrementing counter value. for each flag, one user-defined 20-bit count value can be programmed. when hf 0 or hf 1 count value is equal to the counter value, hf 0 or hf 1 is set on the next rising edge of clock. once the flags are set, they must be reset if they are needed again. the counter will increment by one at the rate of clk and can be reset by hblank. the counter will continue to loop if not reset. hf 0 and hf 1 count value register loading is discussed in the lf interface?. please note, using hblank is the recommended way of clearing hf 0 and hf 1 flags but they can be cleared by reset, normally performed during device initialization. reset will not reset the counter. input/output bias adder the programmable input/output bias adders can be used to subtract or add a 13-bit offset to the data. input and output data formats for the two sections are f igure 11. m atrix m ultiplier and k ey s caler a ' d 13 13 26 26 28 26 20(msb) l rs 13 b ' 20(msb) l rs 13 c ' 20(msb) l rs 13 d ' 20(msb) l rs 13 13 26 13 26 13 26 13 26 13 26 13 26 13 26 13 26 coef bank 4 coef bank 0 13 coef bank 1 coef bank 2 coef bank 5 coef bank 6 coef bank 7 coef bank 8 26 28 26 28 13 26 13 13 13 13 13 13 13 a 13 13 13 13 13 coef bank 3 13 13 13 13 13 13 coef bank 9 26 26 26 26 26 26 b c
devices incorporated LF3370 high-definition video format converter 10 08/21/2000Clds.3370-e video imaging products shown in figure 3. by using inbias 1-0 , the user may select one of four pro- grammed input bias adder values (see figure 8). by using outbias 1-0 , the user may select one of four programmed output bias adder values (see figure 9). a value of 00 on inbias 1-0 /outbias 1-0 selects input/output bias adder register 0. a value of 01 selects input/output bias adder register 1 and so on. inbias 1-0 /outbias 1-0 may be changed every clock cycle if desired. if a bias is not desired, then bits 11 & 12 of configuration register 1 can be set up to independently disable the input and output bias values. thus, effectively zeroing the function. the total pipeline latency from the input to the output for each of the two sections is one clk cycle. input/output bias adder register loading is discussed in the lf interface? section. 3 x 3 matrix multiplier processing almost 550 million colors, three simultaneous 13-bit input and output channels are utilized to implement a 3 x 3- matrix multiplication (triple dot product). each truncated 20-bit output is the sum of all three input words multiplied by the appropriate coefficients (see figure 11). these outputs are then fed into the rsl circuitry (see figure 13). input/output formats are shown in figure 3. for each of the nine multipliers, up to four user-defined 13-bit coefficients can be programmed and selected by ca 1-0 . a value of 00 on ca 1-0 selects coefficient set 0 on each of the 9 coefficient banks. a value of 01 selects coefficient set 1 and so on. ca 1-0 may be changed every clock cycle if desired. coefficient bank loading is discussed in the lf interface?. the total pipeline latency from the input of the matrix multiplier to the output of the rsl circuitry is 6 clk cycles and new output data is subsequently available every clock cycle thereafter. if matrix multiplication is not desired, using the appropriate combination of coefficient values while keeping in mind bit weighting, an identity matrix may be set up to bypass the matrix multiplier section (see also first operation select in the bypass options duscussion). key scaler the key channel is equiped with a 13 x 13-bit key scaler (see figure 11) producing a truncated 20-bit output which is then fed into the rsl circuitry (see figure 13). up to four user-defined 13-bit coefficients can be programmed and selected by ca 1-0 . input/output formats are shown in figure 3. the total pipeline latency from the input of the key scaler to the output of the rsl circuitry is 6 clk cycles and new output data is subsequently available every clock cycle thereafter. if scaling is not desired, load and select a key scaler coefficient value of 1 (see also first operation select in the bypass options duscussion). half-band filter there are two internal half-band filters in the LF3370. these half-band filters can either interpolate, decimate, or pass through data found on channel b and channel c. data on channel a and channel d in this section pass through a programmable 127 x 13-bit delay (see bypass section). the filter section (as show in figure 12) is a fixed-coefficient, linear-phase half-band (low-pass) interpolating/decimating digital filter. the filter in this section is a 55-tap transversal fir with 13-bit coefficients as shown in table 3. the frequency re- sponse (figure 14) is in full compliance with smpte 260m. this section can be configured for 2:1 interpolation, 1:2 decimation, or pass-through mode by setting bits 5-8 in configuration register 0 (see table 5). this section can also be placed before or after the matrix multi- plier by setting bit 4 in configuration register 0 (see table 5). the maximum input and output clock rate this section can operate at is the clk rate. the total internal pipeline latency from the input to the output of this section (including rsl circuitry) as shown in figure 12 is 6 cycles. to perform interpolation, the input data rate of this section will be half of clk rate. please note the maximum output data rate is the clk rate. to perform decima- tion, the output data rate of this section will be half of the input data rate. one output sample is obtained for every two input samples. f igure 12. 1:2 i nterpolation / 2:1 d ecimation h alf -b and f ilters 13 b' b variable length bypass delay 127 x 13-bit interpolation circuit 55-tap fir filter 13 l rs 55-tap fir filter 13 l rs configuration / control registers decimation circuit interpolation circuit decimation circuit variable length bypass delay 127 x 13-bit c 13 c'
devices incorporated video imaging products 11 LF3370 high-definition video format converter 08/21/2000Clds.3370-e once an impulse is clocked into the half- band filter section, the 55-value output response begins after 8 clock cycles and ends after 62 clock cycles. the pipeline latency from the input of an impulse to its corresponding output peak is 35 clock cycles. the input/output formats are always in twos complement format as shown in figure 3. in interpolate mode, the gain of the half-band filter is halved (due to half of the input samples being padded with zeros). a right shifted select window is required to maintain an overall filter gain of 1. it is possible that ringing on the filters output could cause the high order bit (bit f18 in figure 3 - interpolate filter output bit weighting) to become high. if a right shifted select window is used, this f18 bit becomes the sign bit of the selected window C and the output is erroneously considered negative. to ensure that no overflow conditions occur, an internal limiter within each half-band filter monitors its output. during interpolate mode, this limiter clamps the output word to 3ffffh (20-bit maximum positive value ) 2) or c0000h (20-bit maximum negative value ) 2) if a positive or negative overflow occurs respectively. the internal 24-bits of the half-band filter are truncated to 20-bits and then passed to the round section of the rsl circuitry; see rsl section for further details. this section is fully bypassable by use of programmable delays (see bypass options section for further details). look-up table three optional programmable input/ output 1k x 13-bit luts have been provided for channels a, b, and c for various uses such as gamma correction. there are not actually two luts per channel as shown in figures 1 and 2; only one lut per channel can be selected for use at any given time. the latency through a lut section is 2 cycles, regard- less of whether the lut is in use or not. when using a lut, the appropriate addressed value will be passed as an output of the lut section. the gamma lut address can be chosen from any of the 4 possible10-bit words that are window selected from the13-bit input data bus. configuring the desired lut address selector position is accomplished by programming bits 10 & 9 of configura- tion register 1. once the lut select data position is programmed, it is meant to control all three gamma luts. therefore, the address selector positions of the three luts cannot be independently controlled. lut loading is discussed in the l f interface? section. t able 2. s elect f ormats slct 1-0 s 12 s 11 s 10 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 00 f 16 f 15 f 14 f 13 f 12 f 11 f 10 f 9 f 8 f 7 f 6 f 5 f 4 01 f 17 f 16 f 15 f 14 f 13 f 12 f 11 f 10 f 9 f 8 f 7 f 6 f 5 10 f 18 f 17 f 16 f 15 f 14 f 13 f 12 f 11 f 10 f 9 f 8 f 7 f 6 11 f 19 f 18 f 17 f 16 f 15 f 14 f 13 f 12 f 11 f 10 f 9 f 8 f 7 f igure 14. f requency r esponse of f ilter 0 0.1 | s 0.2 | s 0.3 | s 0.4 | s 0.5 | s frequency (normalized) 0 C10 C20 C30 C40 C50 C60 C70 C80 gain (db) f igure 13. rsl c ircuitry ll0 ll3 r0 r3 round s0 s3 select ul0 ul3 20 13 13 limit 2 20 13 20 13 rsl 1-0 from core 13
devices incorporated LF3370 high-definition video format converter 12 08/21/2000Clds.3370-e video imaging products rounding the rounding circuitry found in the matrix multiplier and half-band filter sections work in the same manner. the truncated 20 msbs from the matrix multiplier or half-band filter output may be rounded by being added to the contents of one of the four round regis- ters (see figure 13). each round register is 20 bits wide and user-programmable. this allows the matrix multipliers or half-band filters output to be rounded to any precision required. rsl 1-0 deter- mines which of the four round registers are used in each rounding circuitry. a value of 00 on rsl 1-0 selects round register 0. a value of 01 selects round register 1 and so on. rsl 1-0 may be changed every clock cycle if desired. if rounding is not desired, the user must load and select a round register with value of 0. round register loading is discussed in the lf interface? section. selecting the selecting circuitry found in the matrix multiplier and half-band filter sections work in the same manner. the output word of the matrix multiplier and half- band filter feeding the rsl circuitry is the 20 msbs. however, only 13 bits may be sent to the next section. therefore, the select register determines which 13-bits are passed. there are four select registers; rsl 1-0 determines which of the four select registers are used in each select circuitry (see table 2). a value of 00 on rsl 1-0 selects select register 0. a value of 01 selects select register 1 and so on. rsl 1-0 may be changed every clock cycle if desired. this allows the 13-bit window to be changed every clock cycle. select register loading is discussed in the lf interface? section. limiting the limiting circuitry found in the matrix multiplier and half-band filter sections work in the same manner. the limit registers determine the valid range impulse response out (non-interpolated bit weighing) tap 20-bit (msb) filter out (hex) decimal equivalent 1, 55 ffe35 C0.0008755 2, 54 0 0 3, 53 002d2 0.0013771 4, 52 0 0 5, 51 ffb5c C0.00226593 6, 50 0 0 7, 49 00725 0.0034885 8, 48 0 0 9, 47 ff508 C0.0053558 10, 46 0 0 11, 45 00f95 0.0076084 12, 44 0 0 13, 43 fea10 C0.01071167 14, 42 0 0 15, 41 01e59 0.0148182 16, 40 0 0 17, 39 fd6a8 C0.02018738 18, 38 0 0 19, 37 0393e 0.0279503 20, 36 0 0 21, 35 faf1b C0.0394993 22, 34 0 0 23, 33 0798d 0.05935097 24, 32 0 0 25, 31 f2bd2 C0.10360334 26, 30 0 0 27, 29 28b30 0.3179626 28 (center) 401bc 0.500846862 t able 3. h alf -b and f ilter i mpulse r esponse of output values for each of these two sections. there are four 13-bit limit registers for each section. rsl 1-0 deter- mines which of the four limit registers are used in each limiting circuitry (see figure 13). a value of 00 on rsl 1-0 selects limit register 0. a value of 01 selects limit register 1 and so on. each limit register contains an upper and lower limit value. if the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the matrix multiplier sections or half- band filter sections output. if the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the matrix multiplier sections or half-band filter sections output. rsl 1-0 may be changed every clock cycle if desired thus allowing the limit range to be changed every clock cycle. when loading limit values into the device, the upper limit must be greater than the lower limit. the most negative and most positive values you can load into the limit registers are 0fffh and 1000h. limit register loading is discussed in the lf interface? section. lf interface? the lf interface? is used to load the configuration registers, matrix multi- plier/key scaler coefficient banks, look- up tables, input/output bias registers, rsl registers, hf 0 and hf 1 count values, and horizontal blanking levels. ld is used to enable and disable the lf interface?. when ld goes low, the lf interface? is enabled for data input. the first value fed into the interface on cf 12-0 is an address which determines what the interface is going to load (see table 4). for example, to load address bias adder register 2 of the channel b output bias adder, the first data value into the lf interface? should be 0a02h. to load rsl register 1 for the keyscaler rsl, the first data value should be 1101h. the first address value should be loaded into the interface on the same clock cycle
devices incorporated video imaging products 13 LF3370 high-definition video format converter 08/21/2000Clds.3370-e that latches the high to low transition of ld. the next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defined by the address value. when loading coefficient banks, the interface will expect ten values to be loaded into the device after the address value. the ten values are coefficients 0 through 8 and the keyscale coefficient. when loading configuration or bias registers, the interface will expect one value after the address value. when loading rsl registers, the interface will expect four values after the address value. when loading gamma look-up tables, the interface will expect 1024 values after the address value. when loading hblank flag counts, the interface will expect 2 values after the address value. the coefficient banks, configuration registers, rsl registers, etc., are not loaded with data until all data values for the specified address are loaded into the lf interface. in other words, the coeffi- cient banks are not written until all ten coefficients have been loaded into the lf description address range (hex) coefficient registers 0000 - 0003 configuration registers 0200 - 020a look-up table - channel a 0300 look-up table - channel b 0400 look-up table - channel c 0500 input bias registers - channel a 0600 - 0603 input bias registers - channel b 0700 - 0703 input bias registers - channel c 0800 - 0803 output bias registers - channel a 0900 - 0903 output bias registers - channel b 0a00 - 0a03 output bias registers - channel c 0b00 - 0b03 hf0 count value 0c00 hf1 count value 0d00 matrix mult. rsl registers - channel a 0e00 - 0e03 matrix mult. rsl registers - channel b 0f00 - 0f03 matrix mult. rsl registers - channel c 1000 - 1003 key scaler rsl registers 1100 - 1103 half-band filter rsl registers - channel b 1200 - 1203 half-band filter rsl registers - channel c 1300 - 1303 t able 4. c onfiguration /c ontrol r egisters a ddressing s ummary f igure 15. b ypass b lock d iagram variable length bypass delay (127 x 13-bit ) half-band filter section matrix multiplier and key scaler section lut section output bias section variable length bypass delay (127 x 13-bit ) input bias section 13 input demux section 13 output mux section 13 lut section a, b, c, d w, x, y, z 13 in this example, the matrix-multipler/key scaler section feeds the half-band filter section. this arrangement is reversible. f igure 16. c ore b ypass clk in this example, the output multiplexer is in a mode where the delay through the section is 2 clk cycles. only one channel is shown in this example, however, the other three channels behave in the same manner. the example assumes that the bypass ram length is set to the leng th of the core data path. core data d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 * output* d 13 d 14 d 15 d 16 d 17 datapass b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 d 0 d 1 d 2 d 3 d 4 d 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 d 13 d 14 d 15 bypass data w1: bypass data is output to the output port and replaces core data. w2: core data is output to the output port and replaces bypass data. w1 w2
devices incorporated LF3370 high-definition video format converter 14 08/21/2000Clds.3370-e video imaging products interface?. a rsl register is not written to until all four data words are loaded. after the last data value is loaded, the interface will expect a new address value on the next clock cycle. after the next address value is loaded, data loading will begin again as previously discussed. pause allows the user to effectively slow the rate of data loading through the lf interface?. when pause is high, the lf interface ? is held until pause is returned low. figure 19 shows the effects of pause while loading matrix multiplier/key scaler coefficients. table 28 shows an example of loading a bias value into the input bias adder register. in this example, a bias value of 007fh is loaded into the channel c input bias adder register 1 (0b01h). table 29 shows an example of loading a bias value into the output bias adder register. in this example, a bias value of 0010h is loaded into channel a output bias adder register 3 (0903h). table 30 shows an example of loading data into the matrix multiplier/key scaler coefficient banks. in this example, the following values are loaded into coefficient register set 2 (0002h): 0000h, 0001h, 0002h, 0003h, 0004h, 0005h, 0006h, 0007h, 0008h, and 0009h. table 31 shows an example of loading the hf 0 flag count value. in this example, a 20-bit hf 0 flag count value of b3c27h is loaded into the hf 0 flag count value register (0c00h). the hf 1 flag count value is loaded in the same manner using the appropriate address. table 32 shows an example of loading round/select/limit values. in this example, channel a matrix multiplier register set 0 (0e00h) is loaded with a 20- bit round value of 00020h, a 2-bit select value of 10h, a 13-bit upper limit value of 0fffh, and a 13-bit lower limit value of 1001h. other rsl registers are loaded in the same manner using the appropriate address. bits function description 1-0 look-up table control 00 : disable look-up table channel a 01 : enable look-up table on input 10 : enable look-up table on output 11 : reserved 3-2 look-up table control 00 : disable look-up table channel b 01 : enable look-up table on input 10 : enable look-up table on output 11 : reserved 5-4 look-up table control 00 : disable look-up table channel c 01 : enable look-up table on input 10 : enable look-up table on output 11 : reserved 6 hblank control 0 : disable horizontal blanking option key channel during hblank period 1 : enable horizontal blanking option during hblank period 8-7 data bypass mode w 00 : output channel a to w 12-0 output channel mux control 01 : output channel b to w 12-0 10 : output channel c to w 12-0 11 : output channel d to w 12-0 10-9 look-up table input 00 : select address data [9:0] address selection control 01 : select address data [10:1] 10 : select address data [11:2] 11 : select address data [12:3] 11 input bias disable 0 : enable input bias 1 : disable input bias 12 output bias disable 0 : enable output bias 1 : disable output bias t able 6. c onfiguration r egister 1 C a ddress 201h bits function description 1-0 video input format 00 : reserved 01 : single channel interleaved video 10 : dual channel interleaved video 11 : 3 channel non-interleaved video 3-2 video output format 00 : reserved 01 : single channel interleaved video 10 : dual channel interleaved video 11 : 3 channel non-interleaved video 4 functional arrangement 0 : filter feeds matrix multiplier 1 : matrix multiplier feeds filter 6-5 half-band filter control 00 : pass through filter channel b 01 : interpolate 10 : decimate 11 : bypass filter 8-7 half-band filter control 00 : pass through filter channel c 01 : interpolate 10 : decimate 11 : bypass filter 9 first operation select 0 : normal order of operations 1 : select first operation only 12-10 reserved must be set to zero t able 5. c onfiguration r egister 0 C a ddress 200h
devices incorporated video imaging products 15 LF3370 high-definition video format converter 08/21/2000Clds.3370-e table 33 shows an example of loading a configuration register. in this example, configuration register 0 (0200h) is loaded with 00aeh. this will setup the input section to handle luma on input port a 12-0 and interleaved chroma on the input port b 12-0 . the output section is setup to output rgb on the output ports w 12-0 , x 12-0 , y 12-0 . the functional arrangement is setup in such a way that the half-band filter section is placed before the matrix multiplier section. the half-band filters are setup for 1:2 interpolation and normal order of operations is selected. bypass options core bypass at all times during the normal operation of the LF3370, video data on channels a, b, c, and d are simultaneously being fed from the output of the input demultiplexer into the programmable core bypass delay (see figure 15). this allows users to switch between processed video and unprocessed (bypassed) data on-the-fly. there is a separate core bypass delay for each channel. each core bypass delay can be programmed for a length of 2 up to 129 clk cycles for delay matching between the bypass path and the core as well as other operations. the core bypass delay bypasses the input bias, input lut, half-band filter, matrix multiplier/key scaler section, and output bias and feeds the output multiplexer. loading configuration register 2 programs the length of all four core bypass delays (see table 7). a low state detected on datapass on a rising edge of clock will output by- passed data to the output port on the following rising edge of clk (see figure x). in addition, any of the four bypassed channels can be passed to the w output channel during a bypass event. for this operation, use bits 7 and 8 of configura- tion register 1 (see table 6). half-band filter bypass at all times, while data is being fed into the half-band filter section, channels a, b, c, and key are fed into programmable length delays. when the half-band filter(s) are set to filter bypass mode, that particular channel passes through a programmable delay and is not filtered. since there are only two half-band filters in this section found on channels b and c, channels a and key are passed through their respective programmable delays. please note, when using a single channel video input or video output (interleaved 4:2:2), the core bypass delay must be programmed to double the length [(desired length x 2) C 2)] to properly align data due to the core running at half the clk rate. first operation select first operation select is a bypassing option where you select to use the first functional block (half-band filter or matrix multiplier/key scaler) in any given arrangement. if the device was arranged in such a way that the half-band filter section fed the matrix multiplier/key scaler section and first operation select was enabled, the half-band filter section will be used and the matrix multiplier/ key scaler section will be bypassed. bits function description 6-0 core bypass delay length length of core bypass delay minus 2 12-7 reserved must be set to zero t able 7. c onfiguration r egister 2 C a ddress 202h bits function description 6-0 channel a filter section length of filter bypass delay minus 2 bypass delay length 12-7 reserved must be set to zero t able 8. c onfiguration r egister 3 C a ddress 203h bits function description 6-0 channel b filter section length of filter bypass delay minus 2 bypass delay length 12-7 reserved must be set to zero t able 9. c onfiguration r egister 4 C a ddress 204h bits function description 6-0 key channel filter section length of filter bypass delay minus 2 bypass delay length 12-7 reserved must be set to zero t able 11. c onfiguration r egister 6 C a ddress 206h bits function description 6-0 channel c filter section length of filter bypass delay minus 2 bypass delay length 12-7 reserved must be set to zero t able 10. c onfiguration r egister 5 C a ddress 205h
devices incorporated LF3370 high-definition video format converter 16 08/21/2000Clds.3370-e video imaging products if the device was arranged in such a way that the matrix multiplier/key scaler section fed the half-band filter section and first operation select was enabled, the matrix multiplier/key scaler section will be used and the half-band filter section will be bypassed. unlike in other bypassing options, when a section is bypassed, the total pipeline latency of the device is reduced by the appropriate delay. if the half-band filter section was by- passed by this method, the overall pipeline latency should be reduced by 35 clk cycles. if the matrix multiplier section was bypassed by this method, the overall pipeline latency should be reduced by 6 clk cycles. this function is implemented by configuring bit 9 of configuration register 0. the functional arrangement of the device is determined by configuring bit 4 of configuration register 0. t able 27. l ook -u p t able a ddressing register address (hex) 0 0600 1 0601 2 0602 3 0603 t able 12. c hannel a i nput b ias r egisters register address (hex) 0 0700 1 0701 2 0702 3 0703 t able 13. c hannel b i nput b ias r egisters register address (hex) 0 0800 1 0801 2 0802 3 0803 t able 14. c hannel c i nput b ias r egisters register address (hex) 0 0a00 1 0a01 2 0a02 3 0a03 t able 16. c hannel b o utput b ias r egisters register address (hex) 0 0b00 1 0b01 2 0b02 3 0b03 t able 17. c hannel c o utput b ias r egisters register address (hex) 0 0900 1 0901 2 0902 3 0903 t able 15. c hannel a o utput b ias r egisters register address (hex) 0 1000 1 1001 2 1002 3 1003 t able 20. c hannel c m atrix m ult . rsl r egisters register address (hex) 0 0f00 1 0f01 2 0f02 3 0f03 t able 19. c hannel b m atrix m ult . rsl r egisters register address (hex) 0 0e00 1 0e01 2 0e02 3 0e03 t able 18. c hannel a m atrix m ult . rsl r egisters register address (hex) 0 1200 1 1201 2 1202 3 1203 t able 22. c hannel b h alfband f ilter rsl r egisters register address (hex) 0 1300 1 1301 2 1302 3 1303 t able 23. c hannel c h alfband f ilter rsl r egisters register address (hex) 0 1100 1 1101 2 1102 3 1103 t able 21. k ey c hannel m atrix m ult . rsl r egisters t able 24. hf x c ount v alue r egisters t able 25. h orizontal b lanking l evel a ddress register address (hex) 0 0000 1 0001 2 0002 3 0003 t able 26. m atrix m ult . & s caler c oefficient r egisters channel address (hex) a 0207 b 0208 c 0209 d 020a channel address (hex) a 0300 b 0400 c 0500 count address (hex) 0 0c00 1 0d00
devices incorporated video imaging products 17 LF3370 high-definition video format converter 08/21/2000Clds.3370-e cf 12 cf 11 cf 10 cf 9 cf 8 cf 7 cf 6 cf 5 cf 4 cf 3 cf 2 cf 1 cf 0 address 0000000000010 coef bank 0 0000000000000 coef bank 1 0000000000001 coef bank 2 0000000000010 coef bank 3 0000000000011 coef bank 4 0000000000100 coef bank 5 0000000000101 coef bank 6 0000000000110 coef bank 7 0000000000111 coef bank 8 0000000001000 coef bank 9 0000000001001 t able 30. m atrix m ultiplier /k ey s caler c oefficient b ank l oading f ormat cf 12 cf 11 cf 10 cf 9 cf 8 cf 7 cf 6 cf 5 cf 4 cf 3 cf 2 cf 1 cf 0 address 0111000000000 word 0 r000000100000 word 1 rrr0100000000 word 2 0111111111111 word 3 1000000000001 t able 32. rsl r egister l oading f ormat cf 12 cf 11 cf 10 cf 9 cf 8 cf 7 cf 6 cf 5 cf 4 cf 3 cf 2 cf 1 cf 0 address 0110000000000 word 0 r110000100111 word 1 rrrrr 10110011 t able 31. hf x c ount v alue l oading f ormat cf 12 cf 11 cf 10 cf 9 cf 8 cf 7 cf 6 cf 5 cf 4 cf 3 cf 2 cf 1 cf 0 address 0100100000011 word 0 0000000010000 t able 29. o utput b ias a dder r egister l oading f ormat cf 12 cf 11 cf 10 cf 9 cf 8 cf 7 cf 6 cf 5 cf 4 cf 3 cf 2 cf 1 cf 0 address 0101100000001 word 0 0000001111111 t able 28. i ntput b ias a dder r egister l oading f ormat cf 12 cf 11 cf 10 cf 9 cf 8 cf 7 cf 6 cf 5 cf 4 cf 3 cf 2 cf 1 cf 0 address 0001000000000 word 0 0000010101110 t able 33. c onfiguration r egister l oading f ormat ll 12 ul 12 ll 0 ul 0 s 1 r 19 s 0 r 0 hf 0 hf 19
devices incorporated LF3370 high-definition video format converter 18 08/21/2000Clds.3370-e video imaging products f igure 20. m atrix m ultiplier /k ey s caler c oefficient b ank l oading s equence with pause i mplementation addr 1 coef 0 coef 1 clk ld cf 12-0 w1 w1: matrix multiplier/key scaler coefficient set updated and effective on this active rising clock edge. pause coef 9 f igure 19. m atrix m ultiplier /k ey s caler c oefficient b ank l oading s equence addr 1 coef 0 coef 2 coef 3 coef 4 coef 6 addr 7 coef 8 clk ld cf 12-0 w1: matrix multiplier/key scaler coefficient set updated and effective on this active rising clock edge. w1 coef 5 coef 1 coef 9 f igure 18. l ook -u p t able l oading s equence addr 1 n 0 n 2 n 1023 clk ld cf 11-0 w1: lut updated and effective on this rising clock edge. n 1 n 3 n 4 n 1019 n 1021 n 1020 n 1022 w1 f igure 17. c onfiguration , i nput /o utput b ias a dder , rsl, and hblank l evel r egister l oading s equence addr 1 data 1 addr 3 data 4 config reg rsl register hblank level register clk ld cf 12-0 w2 w1: configuration register updated and effective on this rising clock edge. w3 w4 w2: input or output bias adder register updated and effective on this rising clock edge. w3: rsl register set updated and effective on this rising clock edge. data 1 data 3 data 2 addr 4 data 2 data 1 in/out bias reg addr 2 data 1 w4: horizontal blanking level register updated and effective on this rising clock edge. w1
devices incorporated video imaging products 19 LF3370 high-definition video format converter 08/21/2000Clds.3370-e switching characteristics c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) s witching w aveforms :d ata i/o clk a, b, c, d 12-0 controls t pwh t pwl t cyc (except oe) w, x, y, z 12-0 123456 t h t s a, b, c, d n a, b, c, d n+1 t d t dis high impedance t ena w, x, y, z n - 1 7 w, x, y, z n ca n ca n+1 ca 1-0 oe t hct t sct LF3370C 12 symbol parameter min max t cyc cycle time 12 t pwl clock pulse width low 5 t pwh clock pulse width high 5 t s input setup time 4 t h input hold time 0 t sct setup time control inputs 4 t hct hold time control inputs 0 t d output delay 8 t dis three-state output disable delay (note 11) 10 t ena three-state output enable delay (note 11) 10
devices incorporated LF3370 high-definition video format converter 20 08/21/2000Clds.3370-e video imaging products LF3370C 12 symbol parameter min max t cfs configuration input setup 5.5 t cfh configuration input hold 0 t ls load setup time 4 t lh load hold time 0 t ps pause setup time 4 t ph pause hold time 0 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) s witching w aveforms : lf i nterface tm clk t pwl t pwh t cyc t ls t cfs t cfh address t lh cfa 11C0 lda 12 45 3 cf 1 cf 0 6 pausea t ps t ph ldb pauseb cfb 11C0 cf 2
devices incorporated video imaging products 21 LF3370 high-definition video format converter 08/21/2000Clds.3370-e plastic quad flatpack (q6) LF3370qc12 ordering information 0c to +70c c ommercial s creening speed 12 ns 160-pin gnd bin6 bin7 bin8 bin9 bin10 bin11 bin12 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 ain12 vcc rsl1 rsl0 gnd cf0 cf1 cf2 cf3 cf4 cf5 cf6 cf7 cf8 cf9 cf10 cf11 cf12 bin5 bin4 bin3 bin2 bin1 bin0 cin12 cin11 cin10 cin9 cin8 cin7 cin6 cin5 cin4 cin3 cin2 cin1 cin0 gnd din12 din11 din10 din9 din8 din7 din6 din5 din4 din3 din2 din1 din0 vcc clk gnd vcc gnd ca1 ca0 inbias1 inbias0 outbias1 outbias0 datapass hblank reset sync gnd zout0 zout1 zout2 zout3 zout4 vcc gnd zout5 zout6 zout7 zout8 zout9 vcc gnd zout10 zout11 zout12 yout0 yout1 vcc gnd yout2 yout3 yout4 yout5 yout6 vcc yout7 yout8 yout9 yout10 hf1 wout12 wout11 wout10 wout9 vcc wout8 wout7 wout6 wout5 wout4 gnd wout3 wout2 wout1 wout0 xout12 xout11 vcc gnd xout10 xout9 xout8 xout7 xout6 xout5 vcc gnd xout4 xout3 xout2 xout1 xout0 vcc gnd yout12 yout11 oe 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 ld pause gnd hf0 37 38 39 40 41 42 79 80
devices incorporated LF3370 high-definition video format converter 22 08/21/2000Clds.3370-e video imaging products contact factory for additional information. 1320 orleans drive devices incorporated 800.851.0767 tel. 408.542.5400 408.542.5446 (08:00 17:00 pacific) 408.542.0080 fax. applications hotline sunnyvale, ca 94089 apps@logicdevices.com www.logicdevices.com

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